1. Field of the Invention
This invention relates generally to electronic circuits and, more particularly, to electronic circuits which generate a sequence of pulses with a desired period.
2. Description of the Related Art
Electronic circuits can generate a sequence of pulses which can be used in many applications, such as clocks and pulse generators. In various applications it may be desired to generate a sequence of pulses with a period which is either an integer multiple or a non-integer multiple of a reference clock period. A non-integer multiple can be represented as M/N=P.Q, where M and N are natural numbers and P and Q are integer and decimal numbers, respectively. Hence, M/N is a rational number expressed as a fraction and P.Q is its equivalent expressed as a decimal. In an example, if the reference clock period is 10 ns (i.e. 100 MHz), then to produce a signal with a period of 48.8 ns (i.e. 20.5 MHz), the reference clock period can be multiplied by 4.88 (i.e. M=488, N=100, P=4, and Q=0.88). This is equivalent to dividing the reference clock frequency by 4.88 (i.e. 100 MHz/4.88=20.5 MHz).
Several approaches have been proposed to generate output signals with a period which is a non-integer multiple of a reference period. However, these approaches have jitter which limits their usefulness. Jitter refers to variations in the pulse positions caused by switching between two signals with different phases and appears in the output signal as noise and/or an unintended frequency modulation. Noise typically decreases the signal-to-noise ratio of the system.
Jitter can cause errors in the phase determination of the output signal and, consequently, can reduce the phase margin. The phase of the output signal can be used in many applications, such as analog-to-digital and digital-to-analog converters to define time-points at which the data is sampled. If the phase of the output signal jitters, then there can be errors in the time-points which will affect the overall signal quality.
One way to generate signals with non-integer multiple periods is the rational-rate approach. This approach, as disclosed in U.S. Pat. No. 5,088,057, divides the reference clock frequency by two different integer values to generate two sub-frequencies. The system then switches between the two sub-frequencies to produce an average clock frequency. However, one problem with the rational-rate approach is that the average clock frequency appears to jitter between the phases of the two sub-frequencies. Because the sub-frequencies are generated by dividing by integer numbers, the jitter is on the order of a clock cycle.
Another approach is referred as fractional-frequency divider. As disclosed in U.S. Pat. No. 6,157,694, the system provides several phase-shifted reference signals which have pulse edges shifted over the reference signal period. One pulse edge is outputted at a particular time in response to a trigger signal to provide a high-to-low or a low-to-high pulse edge for the output signal. Hence, the timing of the triggering events determines the frequency of the output signal. However, the fractional-frequency approach also generates jitter in the output signal because the switching is between two phase-shifted signals whose pulse edges, in general, do not always occur at the correct time.
In the rational-rate and fractional frequency approaches, jitter can be reduced by increasing the frequency of the reference signal. Jitter can also be reduced in the fractional frequency approach by increasing the number of phase-shifted signals. However, increasing the reference frequency and the number of phase-shifted signals increases the complexity and cost of the circuitry. Consequently, there is a need for a frequency synthesizer which provides an output signal with an arbitrary period and less jitter, using a lower frequency reference signal and fewer phase shifted signals.